<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Yiyun He</style></author><author><style face="normal" font="default" size="100%">Huang, Zifeng</style></author><author><style face="normal" font="default" size="100%">Ming Li</style></author><author><style face="normal" font="default" size="100%">Runsheng WANG</style></author><author><style face="normal" font="default" size="100%">Cheng, Zhe</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Thermal Conductivity Mapping of Interconnects and Active Layers of Logic Chips</style></title><secondary-title><style face="normal" font="default" size="100%">EDTM</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2026</style></year></dates><publisher><style face="normal" font="default" size="100%">IEEE</style></publisher><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>