<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>10</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Yufei Ma</style></author><author><style face="normal" font="default" size="100%">Minkyu Kim</style></author><author><style face="normal" font="default" size="100%">Yu Cao</style></author><author><style face="normal" font="default" size="100%">Sarma Vrudhula</style></author><author><style face="normal" font="default" size="100%">Jae-Sun Seo</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">End-to-End Scalable FPGA Accelerator for Deep Residual Networks</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE International Symposium on Circuits and Systems (ISCAS)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2017</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://ieeexplore.ieee.org/document/8050344</style></url></web-urls></urls><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>