<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>10</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Ying Liu#</style></author><author><style face="normal" font="default" size="100%">Yufei Ma#</style></author><author><style face="normal" font="default" size="100%">Ninghui Shang</style></author><author><style face="normal" font="default" size="100%">Tianhao Zhao</style></author><author><style face="normal" font="default" size="100%">Chen, Peiyu</style></author><author><style face="normal" font="default" size="100%">Wu, Meng</style></author><author><style face="normal" font="default" size="100%">Ru, Jiayoon</style></author><author><style face="normal" font="default" size="100%">Tianyu Jia</style></author><author><style face="normal" font="default" size="100%">Le Ye*</style></author><author><style face="normal" font="default" size="100%">Zhixuan Wang*</style></author><author><style face="normal" font="default" size="100%">Ru HUANG</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflowand Sparsity-Adaptive In-Memory Computing</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE International Solid-State Circuits Conference (ISSCC 2024)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2024</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://ieeexplore.ieee.org/document/10454472</style></url></web-urls></urls><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>