My recent research focuses on developing energy-efficient, programmable and reliable hardware for domain-specific applications, such as AI, autonomous driving. I have general interest in VLSI design and computer architecture areas. Here are some project examples.
Cognitive Heterogeneous SoC Design for Autonomous Driving
In this project, we develop a domain-specific SoC for next generation smart, connected autonomous vehicles. To push the real-time performance and energy-efficiency, the SoC is designed with highly heterogeneous, including the general-purpose CPU processors, AI accelerators, and other specialized hardware accelerators. The SoC design adopts agile HLS design methodology, and based on the open-source Embedded Scalable Platform (ESP).
Reconfigurable and Programmable CPU/NN Architectures for Edge AI
The strong demand for AI at edge devices leads to the popularity of CPU+AI SoC architecture. However, the low utilization of AI core and data transfer between cores often becomes the SoC bottleneck in end-to-end applications. In Neural CPU, we proposed a reconfigurable architecture solution to achieve performance improvement and energy saving. In FlexACC, we proposed a application-specific ISA to tightly couple the general-purpose RISC-V instructions with DNN instructions for flexible DNN inference.
Reliability Analysis and Protection for Safety-Critical Aerial Machines
The aerial drones or robots have to operate robustly in the highly dynamic environments. In this project, we develop an end-to-end fault injection and detection framework at system level for different applications. Through extensive reliability analysis, we explore fault resilient and energy efficient hardware design to improve the system performance and robustness.
Instruction-Driven Adaptive Clocking through HW/SW Co-Design
With the hardware/software co-design method, we observed there is strong correlation between runtime processor instructions (accelerator operands) and the dynamic logic delays. Therefore, we developed a series of advanced instruction-driven adaptive clocking for CPU, GPU, and AI accelerators to dynamic adjust clock and boost the performance.
Fully Integrated Power Management Circuits with Resonant Switching
Targeting for ultra-low-power applications, in this project, we developed the fastest fully-integrated power converters with resonant switching techniques to achieve state-of-art power efficiency and power density for edge devices.