<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">W. Tang*</style></author><author><style face="normal" font="default" size="100%">S.-G. Cho*</style></author><author><style face="normal" font="default" size="100%">T. T. Hoang*</style></author><author><style face="normal" font="default" size="100%">J. Botimer</style></author><author><style face="normal" font="default" size="100%">W. Q. Zhu</style></author><author><style face="normal" font="default" size="100%">C. -C. Chang</style></author><author><style face="normal" font="default" size="100%">C.-H. Lu</style></author><author><style face="normal" font="default" size="100%">Zhu, J.</style></author><author><style face="normal" font="default" size="100%">Tao, Y.</style></author><author><style face="normal" font="default" size="100%">T. Wei</style></author><author><style face="normal" font="default" size="100%">N. K. Motwani</style></author><author><style face="normal" font="default" size="100%">M. Yalamanchi</style></author><author><style face="normal" font="default" size="100%">R. Yarlagadda</style></author><author><style face="normal" font="default" size="100%">S. Kale</style></author><author><style face="normal" font="default" size="100%">M. Flanigan</style></author><author><style face="normal" font="default" size="100%">A. Chan</style></author><author><style face="normal" font="default" size="100%">T. Tran</style></author><author><style face="normal" font="default" size="100%">S. Shumarayev</style></author><author><style face="normal" font="default" size="100%">Z. Zhang</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Arvon: A heterogeneous SiP integrating a 14nm FPGA and two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 interface to provide versatile workload acceleration</style></title><secondary-title><style face="normal" font="default" size="100%">2023 Symposium on VLSI Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2023</style></year></dates><publisher><style face="normal" font="default" size="100%">IEEE</style></publisher><pages><style face="normal" font="default" size="100%">C7-1</style></pages><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>