<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>13</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Tao, Yaoyu</style></author><author><style face="normal" font="default" size="100%">Kwong, Joyce</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">LDPC post-processor architecture and method for low error floor conditions</style></title></titles><dates><year><style  face="normal" font="default" size="100%">2017</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://patents.google.com/patent/US9793923B2/en</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">Google Patents</style></publisher><language><style face="normal" font="default" size="100%">eng</style></language><notes><style face="normal" font="default" size="100%">&lt;p&gt;US Patent 9,793,923&lt;/p&gt;</style></notes></record></records></xml>