@conference {tao20193,
	title = {Arvon: A heterogeneous SiP integrating a 14nm FPGA and two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 interface to provide versatile workload acceleration},
	booktitle = {2023 Symposium on VLSI Circuits},
	year = {2023},
	pages = {C7-1},
	publisher = {IEEE},
	organization = {IEEE},
	author = {W. Tang* and S.-G. Cho* and T. T. Hoang* and J. Botimer and W. Q. Zhu and C. -C. Chang and C.-H. Lu and Zhu, J. and Tao, Y. and T. Wei and N. K. Motwani and M. Yalamanchi and R. Yarlagadda and S. Kale and M. Flanigan and A. Chan and T. Tran and S. Shumarayev and Z. Zhang}
}
