This paper presents a hybrid 4th-order delta-sigma modulator (DSM). It combines a continuous-time (CT) loop filter and a discrete-time (DT) passive 2nd-order noise-shaping SAR (NSSAR). Since the 2nd-order NS-SAR is robust against PVT variation, the stability of this 4th-order DSM is similar to that of a 2nd-order CT-DSM. The CT loop filter is based on single-amplifier bi-quad (SAB) structure. As a result, only one OTA is used to achieve 4th-order noise shaping, leading to a high power efficiency. Moreover, this work implements both excess loop delay (ELD) compensation and an input feedforward path inside the NS-SAR in the charge domain, further reducing the circuit complexity and the OTA power. Overall, this work achieves 81 dB SNDR over 12.5 MHz with 3.7 mW power, leading to a Schreier FoM of 176 dB.
This letter presents a 3T eDRAM in-memory physically unclonable function (PUF) for low-cost Internet of Things (IoT) applications. The proposed design integrates PUF to eDRAM with a small
peripheral overhead. With the subthreshold leakage of the bit-cell read path exploited as the entropy source, two adjacent 3T eDRAMs (with 2 × 197 F2 = 394 F2 area) race to generate the key bit. To overcome voltage and temperature variations, the spatial majority voting (SMV) is adopted. Implemented in 65-nm CMOS, the proposed eDRAM PUF achieves <0.35% bit error rate (BER) across a voltage range of 1.0–1.2 V and temperature range of 0 ◦C–60 ◦C, presenting a low-cost and robust solution for IoT security.