<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Lao, Yunhong</style></author><author><style face="normal" font="default" size="100%">Wei, Jin</style></author><author><style face="normal" font="default" size="100%">Wang, Maojun</style></author><author><style face="normal" font="default" size="100%">Yu, Jingjing</style></author><author><style face="normal" font="default" size="100%">Fan, Zetao</style></author><author><style face="normal" font="default" size="100%">Yang, Junjie</style></author><author><style face="normal" font="default" size="100%">Cui, Jiawei</style></author><author><style face="normal" font="default" size="100%">Teng Li</style></author><author><style face="normal" font="default" size="100%">Yang, Han</style></author><author><style face="normal" font="default" size="100%">Nuo, Muqin</style></author><author><style face="normal" font="default" size="100%">Jiang, Qimeng</style></author><author><style face="normal" font="default" size="100%">Tang, Gaofei</style></author><author><style face="normal" font="default" size="100%">Shen, Bo</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Split-p-GaN Gate HEMT With Suppressed Negative Vth Shift and Enhanced Robustness Against False Turn-On</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Electron Device Letters</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">Electron devices</style></keyword><keyword><style  face="normal" font="default" size="100%">false turn-on</style></keyword><keyword><style  face="normal" font="default" size="100%">gate/drain coupled barrier lowering (GDCBL) effect</style></keyword><keyword><style  face="normal" font="default" size="100%">HEMTs</style></keyword><keyword><style  face="normal" font="default" size="100%">Integrated circuit reliability</style></keyword><keyword><style  face="normal" font="default" size="100%">Logic gates</style></keyword><keyword><style  face="normal" font="default" size="100%">Negative Vₜₕ shift</style></keyword><keyword><style  face="normal" font="default" size="100%">Robustness</style></keyword><keyword><style  face="normal" font="default" size="100%">Silicon</style></keyword><keyword><style  face="normal" font="default" size="100%">split-p-GaN gate</style></keyword><keyword><style  face="normal" font="default" size="100%">Switches</style></keyword><keyword><style  face="normal" font="default" size="100%">Switching circuits</style></keyword><keyword><style  face="normal" font="default" size="100%">Threshold voltage</style></keyword><keyword><style  face="normal" font="default" size="100%">Transistors</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2025</style></year></dates><number><style face="normal" font="default" size="100%">4</style></number><volume><style face="normal" font="default" size="100%">46</style></volume><pages><style face="normal" font="default" size="100%">628-631</style></pages><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>