<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Gao, Jingnan</style></author><author><style face="normal" font="default" size="100%">Jin, Yufeng</style></author><author><style face="normal" font="default" size="100%">Hao, Yilong</style></author><author><style face="normal" font="default" size="100%">Xie, Bing</style></author><author><style face="normal" font="default" size="100%">Wen, Cheng P.</style></author><author><style face="normal" font="default" size="100%">Shen, Bo</style></author><author><style face="normal" font="default" size="100%">Wang, Maojun</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Gate-Recessed Normally OFF GaN MOSHEMT With High-Temperature Oxidation/Wet Etching Using LPCVD Si3N4 as the Mask</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE TRANSACTIONS ON ELECTRON DEVICES</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">GaN metal-oxide-semiconductor high-electron-mobility transistor (MOSHEMT)</style></keyword><keyword><style  face="normal" font="default" size="100%">low-pressure chemical vapor deposition (LPCVD) Si3N4</style></keyword><keyword><style  face="normal" font="default" size="100%">normally off</style></keyword><keyword><style  face="normal" font="default" size="100%">oxidation</style></keyword><keyword><style  face="normal" font="default" size="100%">passivation</style></keyword><keyword><style  face="normal" font="default" size="100%">wet etching</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2018</style></year><pub-dates><date><style  face="normal" font="default" size="100%">MAY</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">5</style></number><publisher><style face="normal" font="default" size="100%">IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC</style></publisher><pub-location><style face="normal" font="default" size="100%">445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA</style></pub-location><volume><style face="normal" font="default" size="100%">65</style></volume><pages><style face="normal" font="default" size="100%">1728-1733</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">A gate-recessed normally OFF GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. The LPCVD Si3N4 serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si3N4 as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843 cm(2)/V . s, and low-channel resistance of 0.89 Omega . mm are achieved for a normally OFF channel with L-G = 1.5 mu m. For 3 mu m L-GD, the fabricated devices exhibit a threshold voltage (Vth) of 1.35 V, a maximum drain current of similar to 500 mA/mm, a high ON/OFF current ratio of similar to 1010, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of similar to 10-7 mA/mm up to 10 V. A high Baliga's figure of merit of 1.26 GW/cm(2) is achieved in devices with 10-mu m gate-drain distance.</style></abstract><work-type><style face="normal" font="default" size="100%">Article</style></work-type><custom7><style face="normal" font="default" size="100%">000430698900010</style></custom7></record></records></xml>