<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Sang, Fei</style></author><author><style face="normal" font="default" size="100%">Wang, Maojun</style></author><author><style face="normal" font="default" size="100%">Ming Tao</style></author><author><style face="normal" font="default" size="100%">Liu, Shaofei</style></author><author><style face="normal" font="default" size="100%">Min Yu</style></author><author><style face="normal" font="default" size="100%">Xie, Bing</style></author><author><style face="normal" font="default" size="100%">Wen, Cheng P.</style></author><author><style face="normal" font="default" size="100%">Wang, Jingyan</style></author><author><style face="normal" font="default" size="100%">Wu, Wengang</style></author><author><style face="normal" font="default" size="100%">Hao, Yilong</style></author><author><style face="normal" font="default" size="100%">Shen, Bo</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Time-dependent threshold voltage drift induced by interface traps in normally-off GaN MOSFET with different gate recess technique</style></title><secondary-title><style face="normal" font="default" size="100%">APPLIED PHYSICS EXPRESS</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2016</style></year><pub-dates><date><style  face="normal" font="default" size="100%">SEP</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">9</style></number><volume><style face="normal" font="default" size="100%">9</style></volume><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">The time-dependent threshold voltage drift induced by fast interface traps in a fully gate-recessed normally-off GaN MOSFET is studied. It is found that the degree and time scale of the shift in threshold voltage are consistent with the density and time constant of interface traps at the MOS interface. The device based on wet etching delivers higher interface quality and threshold voltage stability than that based on dry etching. Nitrogen deficiency and high oxygen coverage are considered to be the origins of the high interface trap density in the MOSFET fabricated by dry etching. (C) 2016 The Japan Society of Applied Physics</style></abstract><custom7><style face="normal" font="default" size="100%">000383983700001</style></custom7></record></records></xml>