Characterization of 880 V Normally Off GaN MOSHEMT on Silicon Substrate Fabricated With a Plasma-Free, Self-Terminated Gate Recess Process - Ming Tao; Liu, Shaofei; Xie, Bing; Wen, Cheng P.; Wang, Jinyan; Hao, Yilong; Wu, Wengang; Cheng, Kai; Shen, Bo; Wang, Maojun (IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018)
In this paper, we report the device performance of a high-voltage enhancement-mode (E-mode) GaN MOSHEMT on silicon substrate. Normally off operation is realized by a self-terminated precision gate recess process on an optimized high-electronmobility transistor structure. The GaN MOSHEMT is fully pinched off at zero gate bias, suggesting a ``true'' normally off operation. The threshold voltage is 0.4 V with a drain current density of 1 mu A/mm as the criteria. The device with 15-mu m gate-drain distance and 100-mu m gate width exhibits a maximum drain current of 356 mA/mm at 8-V gate bias. The on/off current ratio of the device is larger than 1010 with a subthreshold slope of 80 mV/dec. The gate leakage current is below 10-7 mA/mm up to 9-V gate bias. The off-state breakdown voltage (BV) is as high as 1528 V (880 V) measured with floating (grounded) silicon substrate at a drain leakage current criterion of 5 mu A/mm. The specific on-resistance (R-ON,R-SP) of the device is 2.79 m Omega.cm(2), and the power figure of merit (BV2/R-ON,R-SP) is 277 MW/cm(2). High-voltage pulsed I-V measurement indicates that the dynamic on-resistance is only 1.6 times the static one with a pulsewidth of 10 mu s at 400-V off-state quiescent drain bias. The high performance of the normally off GaN MOSHEMT is supposed to benefit from the high quality low pressure chemical vapor deposition Si3N4 passivation layer and the advanced E-mode device fabrication process.
Keywords: Dynamic on-resistance; GaN high-electron mobility transistor (HEMT); gate recess; MOSHEMT; normally off