@article {10.1063/5.0315801,
	title = {Enhancement-mode GaN p-FET with p-NiO/p-GaN heterojunction gate featuring improved threshold voltage stability and channel conductivity based on low interface trap density},
	journal = {Applied Physics Letters},
	volume = {128},
	number = {17},
	year = {2026},
	month = {04},
	pages = {173505},
	abstract = {Enhancement-mode (E-mode) p-channel field-effect transistors (p-FETs) remain challenging for GaN complementary logic (CL) technology due to their unstable threshold voltage (Vth), low current density, and large on-resistance (RON) at 6 V CL-compatible operation. In this work, we demonstrate a high-performance E-mode GaN p-FET with a p-NiO/p-GaN heterojunction gate. Notably, the suppressed Vth shift and improved channel conductivity were simultaneously achieved in the E-mode channel. The improvement is primarily due to the type-II band alignment at the p-NiO/p-GaN interface. This structure reduces band overlap, resulting in a low interface trap density (DT) of 3.29{\textendash}5.71 {\texttimes} 1010 cm-2 eV-1 as measured by the sub-bandgap photo-assisted capacitance{\textendash}voltage method. The fabricated device with LG/LGS/LGD = 1.5/3/3 μm exhibits a Vth of -0.6 V with a minimal hysteresis of 0.02 V and maximum shift of 0.04 V under stress, a ID of 5.5 mA/mm, a RON of 0.47 k Ω mm, and a transconductance (gm) of 1.8 mS/mm for 6 V CL-compatible operation.},
	issn = {0003-6951},
	doi = {10.1063/5.0315801},
	url = {https://doi.org/10.1063/5.0315801},
	author = {Wang, Jinbing and Wang, Maojun and Wang, Pengfei and Wei, Jin and Wang, Jinyan and Zhang, Xun and Feng, Yuxia and Sun, Na and Pei, Xinyi and Ye, Jiandong and Chen, Kevin J. and Yang, Han and Shen, Bo}
}
