@article {10856268,
	title = {Split-p-GaN Gate HEMT With Suppressed Negative Vth Shift and Enhanced Robustness Against False Turn-On},
	journal = {IEEE Electron Device Letters},
	volume = {46},
	number = {4},
	year = {2025},
	pages = {628-631},
	keywords = {Electron devices, false turn-on, gate/drain coupled barrier lowering (GDCBL) effect, HEMTs, Integrated circuit reliability, Logic gates, Negative Vₜₕ shift, Robustness, Silicon, split-p-GaN gate, Switches, Switching circuits, Threshold voltage, Transistors},
	doi = {10.1109/LED.2025.3535601},
	author = {Lao, Yunhong and Wei, Jin and Wang, Maojun and Yu, Jingjing and Fan, Zetao and Yang, Junjie and Cui, Jiawei and Teng Li and Yang, Han and Nuo, Muqin and Jiang, Qimeng and Tang, Gaofei and Shen, Bo}
}
