@article { ISI:000466190700008,
	title = {A Compact Model for Border Traps in Lateral MOS Devices with Large Channel Resistance},
	journal = {IEEE ELECTRON DEVICE LETTERS},
	volume = {40},
	number = {5},
	year = {2019},
	month = {MAY},
	pages = {694-697},
	publisher = {IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC},
	type = {Article},
	address = {445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA},
	abstract = {In this letter, a distributed network model describing the effects of the border traps and distributed channel resistance on the impedance frequency dispersion of lateral MOS devices is proposed. The proposed model is verified using a gate recessed, normally-off Al2O3/GaN MOSFET structure operating as a MOS diode. The measured frequency-dependent capacitance and conductance curves of the MOS diode over a wide frequency range are found to be in good agreement with the proposed model. According to the intrinsic property of border traps to the ac signal, the proposed model is further modified to get the spatial distribution of border traps. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures.},
	keywords = {border traps, channel resistance, impedance frequency dispersion, Lateral MOS devices},
	issn = {0741-3106},
	doi = {10.1109/LED.2019.2905857},
	author = {Yin, Ruiyuan and Li,Yue and Wei Lin and Wen, Cheng P. and Hao, Yilong and Fu, Yunyi and Wang, Maojun}
}
