@article { ISI:000430698900010,
	title = {Gate-Recessed Normally OFF GaN MOSHEMT With High-Temperature Oxidation/Wet Etching Using LPCVD Si3N4 as the Mask},
	journal = {IEEE TRANSACTIONS ON ELECTRON DEVICES},
	volume = {65},
	number = {5},
	year = {2018},
	month = {MAY},
	pages = {1728-1733},
	publisher = {IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC},
	type = {Article},
	address = {445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA},
	abstract = {A gate-recessed normally OFF GaN metal-oxide-semiconductor high-electron-mobility transistor on silicon substrate has been fabricated using a self-terminated, plasma-free oxidation and wet etching process with pre-recess low-pressure chemical vapor deposition (LPCVD) Si3N4 passivation layer. The LPCVD Si3N4 serves the dual role of gate-recess mask and passivation layer. Unlike conventional oxidation etching process using Si3N4 as post gate-recess passivation, the gate channel region was prevented from additional plasma bombardment during the gate window re-opening. As a result, a high-effective channel mobility of 843 cm(2)/V . s, and low-channel resistance of 0.89 Omega . mm are achieved for a normally OFF channel with L-G = 1.5 mu m. For 3 mu m L-GD, the fabricated devices exhibit a threshold voltage (Vth) of 1.35 V, a maximum drain current of similar to 500 mA/mm, a high ON/OFF current ratio of similar to 1010, and 560-V OFF-state breakdown voltage together with a low-forward gate leakage current of similar to 10-7 mA/mm up to 10 V. A high Baliga{\textquoteright}s figure of merit of 1.26 GW/cm(2) is achieved in devices with 10-mu m gate-drain distance.},
	keywords = {GaN metal-oxide-semiconductor high-electron-mobility transistor (MOSHEMT), low-pressure chemical vapor deposition (LPCVD) Si3N4, normally off, oxidation, passivation, wet etching},
	issn = {0018-9383},
	doi = {10.1109/TED.2018.2812215},
	author = {Gao, Jingnan and Jin, Yufeng and Hao, Yilong and Xie, Bing and Wen, Cheng P. and Shen, Bo and Wang, Maojun}
}
