<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Mukherjee, Abhishek</style></author><author><style face="normal" font="default" size="100%">Gandara, Miguel</style></author><author><style face="normal" font="default" size="100%">Yang, Xiangxing</style></author><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Xiyuan TANG</style></author><author><style face="normal" font="default" size="100%">Hsu, Chen-Kai</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2021</style></year><pub-dates><date><style  face="normal" font="default" size="100%">Feb</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">2</style></number><volume><style face="normal" font="default" size="100%">56</style></volume><pages><style face="normal" font="default" size="100%">476-487</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This work introduces a second-order voltage-controlled oscillator (VCO)-based continuous-time delta-sigma modulator (CTDSM) that incorporates a distributed-input VCO as the second-stage integrator and quantizer. The distributed-input VCO topology virtually eliminates the VCO&amp;#039;s voltage-to-frequency (V-F) parasitic pole. One of the key ideas of this article is to demonstrate the use of a capacitive-π network in the modulator&amp;#039;s loop filter to break the constraint between the size of the modulator&amp;#039;s inner capacitive digital-to-analog converter (DAC) and the factor by which the front-end Gm-C integrator is impedance scaled. This, in turn, helps to significantly reduce both analog and digital powers. The prototype chip has been fabricated in a 40-nm CMOS process. Despite not using any DAC calibration or explicit dynamic element matching (DEM) circuits, the worst case spurious-free dynamic range (SFDR) is -82 dBc across the signal bandwidth. The fabricated CTDSM achieves a 71.8-dB signal-to-noise-and-distortion ratio (SNDR) and a 74.5-dB dynamic range (DR) in a 10-MHz bandwidth at 655 MS/s, yielding an SNDR-based Walden figure of merit (FoM) of 45.6 fJ/step, an SNDR-based Schreier FoM of 167.2 dB, and a DR-based Schreier FoM of 169.9 dB.</style></abstract></record></records></xml>