<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Wei Shi</style></author><author><style face="normal" font="default" size="100%">Liu, Jiaxin</style></author><author><style face="normal" font="default" size="100%">Mukherjee, Abhishek</style></author><author><style face="normal" font="default" size="100%">Yang, Xiangxing</style></author><author><style face="normal" font="default" size="100%">Xiyuan TANG</style></author><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Zhao, Wenda</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 3.7mW 12.5MHz 81dB-SNDR 4th-Order Continuous-time DSM with Single-OTA and 2nd-Order Noise-shaping SAR</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Open Journal of the Solid-State Circuits Society</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2022</style></year></dates><pages><style face="normal" font="default" size="100%">1-1</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This paper presents a hybrid 4th-order delta-sigma modulator (DSM). It combines a continuous-time (CT) loop filter and a discrete-time (DT) passive 2nd-order noise-shaping SAR (NSSAR). Since the 2nd-order NS-SAR is robust against PVT variation, the stability of this 4th-order DSM is similar to that of a 2nd-order CT-DSM. The CT loop filter is based on single-amplifier bi-quad (SAB) structure. As a result, only one OTA is used to achieve 4th-order noise shaping, leading to a high power efficiency. Moreover, this work implements both excess loop delay (ELD) compensation and an input feedforward path inside the NS-SAR in the charge domain, further reducing the circuit complexity and the OTA power. Overall, this work achieves 81 dB SNDR over 12.5 MHz with 3.7 mW power, leading to a Schreier FoM of 176 dB.</style></abstract></record></records></xml>