<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Lu, Nanshu</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 1-V 0.25- $μ \textW$ Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2018</style></year><pub-dates><date><style  face="normal" font="default" size="100%">March</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">3</style></number><volume><style face="normal" font="default" size="100%">53</style></volume><pages><style face="normal" font="default" size="100%">896-905</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This paper presents a highly power-efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves six-time current reuse, thereby significantly boosting the transconductance and lowering noise but without increasing the current consumption. A novel biasing scheme is devised to ensure robust operation under 1-V supply. A prototype in 180-nm CMOS has 5.5-μVrms noise within 10-kHz BW while consuming only 0.25-μW power, leading to a noise efficiency factor of 1.07, which is the best among reported amplifiers.</style></abstract></record></records></xml>