<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Xiyuan TANG</style></author><author><style face="normal" font="default" size="100%">Yang, Xiangxing</style></author><author><style face="normal" font="default" size="100%">Zhao, Wenda</style></author><author><style face="normal" font="default" size="100%">Hsu, Chen-Kai</style></author><author><style face="normal" font="default" size="100%">Liu, Jiaxin</style></author><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Mukherjee, Abhishek</style></author><author><style face="normal" font="default" size="100%">Wei Shi</style></author><author><style face="normal" font="default" size="100%">Li, Shaolan</style></author><author><style face="normal" font="default" size="100%">Pan, David Z.</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2020</style></year><pub-dates><date><style  face="normal" font="default" size="100%">Dec</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">12</style></number><volume><style face="normal" font="default" size="100%">55</style></volume><pages><style face="normal" font="default" size="100%">3248-3259</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only 107 μW. It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.</style></abstract></record></records></xml>