<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Zhao, Wenda</style></author><author><style face="normal" font="default" size="100%">Li, Shaolan</style></author><author><style face="normal" font="default" size="100%">Xu, Biying</style></author><author><style face="normal" font="default" size="100%">Yang, Xiangxing</style></author><author><style face="normal" font="default" size="100%">Xiyuan TANG</style></author><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Lu, Nanshu</style></author><author><style face="normal" font="default" size="100%">Pan, David Z.</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- $ΔΣ$ M Structure</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2020</style></year><pub-dates><date><style  face="normal" font="default" size="100%">March</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">3</style></number><volume><style face="normal" font="default" size="100%">55</style></volume><pages><style face="normal" font="default" size="100%">666-679</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)-ΔΣ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts&amp;#039; counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented to enable a highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40-nm CMOS, the prototype readout achieves 78-dB SNDR in 10-kHz bandwidth, consuming 4.68 μW and 0.025-mm2 active area. With 172-dB Schreier figure of merit, its efficiency advances the state-of-the-art VCO-based readouts by 50×.</style></abstract></record></records></xml>