<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Xiyuan TANG</style></author><author><style face="normal" font="default" size="100%">Li, Shaolan</style></author><author><style face="normal" font="default" size="100%">Yang, Xiangxing</style></author><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Zhao, Wenda</style></author><author><style face="normal" font="default" size="100%">Williams, Randall P.</style></author><author><style face="normal" font="default" size="100%">Liu, Jiaxin</style></author><author><style face="normal" font="default" size="100%">Tan, Zhichao</style></author><author><style face="normal" font="default" size="100%">Hall, Neal A.</style></author><author><style face="normal" font="default" size="100%">Pan, David Z.</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2020</style></year><pub-dates><date><style  face="normal" font="default" size="100%">Nov</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">11</style></number><volume><style face="normal" font="default" size="100%">55</style></volume><pages><style face="normal" font="default" size="100%">3064-3075</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This article presents an incremental two-step capacitance-to-digital converter (CDC) with a time-domain ΔΣ modulator (TDΔΣM). Unlike the classic two-step CDCs, this work replaces the operational transconductance amplifier (OTA)-based active-RC integrator by a voltage-controlled oscillator (VCO)-based integrator, which is mostly digital and low-power. Featuring the infinite dc gain and intrinsic quantization in phase domain, this TDΔΣM enables a CDC design achieving 76-dB SNDR while requiring only a first-order loop, and a low oversampling ratio (OSR) of 15. Fabricated in 40-nm CMOS technology, the prototype CDC achieves a resolution of 0.29 fF while dissipating only 0.083 nJ/conversion, which improves the energy efficiency by over two times comparing to the similar performance designs.</style></abstract></record></records></xml>