<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Yi ZHONG</style></author><author><style face="normal" font="default" size="100%">Li, Shaolan</style></author><author><style face="normal" font="default" size="100%">Xiyuan TANG</style></author><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Zhao, Wenda</style></author><author><style face="normal" font="default" size="100%">Wu, Siliang</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A Second-Order Purely VCO-Based CT $ΔΣ$ ADC Using a Modified DPLL Structure in 40-nm CMOS</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Journal of Solid-State Circuits</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2020</style></year><pub-dates><date><style  face="normal" font="default" size="100%">Feb</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">2</style></number><volume><style face="normal" font="default" size="100%">55</style></volume><pages><style face="normal" font="default" size="100%">356-368</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) ΔΣ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply.</style></abstract></record></records></xml>