<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Mukherjee, Abhishek</style></author><author><style face="normal" font="default" size="100%">Gandara, Miguel</style></author><author><style face="normal" font="default" size="100%">Xu, Biying</style></author><author><style face="normal" font="default" size="100%">Li, Shaolan</style></author><author><style face="normal" font="default" size="100%">Shen, Linxiao</style></author><author><style face="normal" font="default" size="100%">Xiyuan TANG</style></author><author><style face="normal" font="default" size="100%">Pan, David</style></author><author><style face="normal" font="default" size="100%">Sun, Nan</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $ΔΣ$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO</style></title><secondary-title><style face="normal" font="default" size="100%">IEEE Solid-State Circuits Letters</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2019</style></year><pub-dates><date><style  face="normal" font="default" size="100%">Jan</style></date></pub-dates></dates><number><style face="normal" font="default" size="100%">1</style></number><volume><style face="normal" font="default" size="100%">2</style></volume><pages><style face="normal" font="default" size="100%">1-4</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This letter presents a high-speed closed-loop capacitive-input voltage controlled oscillators (VCO)-based continuous-time delta sigma modulator (CTDSM) using a novel fully differential VCO topology whose parasitic pole is inherently located at a very high frequency, regardless of the number of inverters in the ring VCO. The mitigation of the parasitic pole is achieved by splitting the VCO&amp;#039;s input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO&amp;#039;s input capacitance. A single pair of pseudo-resistors is used for providing dc negative feedback in the CTDSM. The prototype first-order 63-stage VCO-based CTDSM is fabricated in 40-nm CMOS and occupies a core area of 0.02 mm2 while achieving 63.1-dB dynamic range in 480 kHz-20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors&amp;#039; best knowledge, this is also the first work to demonstrate the capacitive input in a high-speed CTDSM, without using chopping.</style></abstract></record></records></xml>