@article {8945232,
	title = {A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- $ΔΣ$ M Structure},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {55},
	number = {3},
	year = {2020},
	month = {March},
	pages = {666-679},
	abstract = {This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)-ΔΣ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts\&$\#$039; counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented to enable a highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40-nm CMOS, the prototype readout achieves 78-dB SNDR in 10-kHz bandwidth, consuming 4.68 μW and 0.025-mm2 active area. With 172-dB Schreier figure of merit, its efficiency advances the state-of-the-art VCO-based readouts by 50{\texttimes}.},
	issn = {1558-173X},
	doi = {10.1109/JSSC.2019.2959479},
	author = {Zhao, Wenda and Li, Shaolan and Xu, Biying and Yang, Xiangxing and Xiyuan TANG and Shen, Linxiao and Lu, Nanshu and Pan, David Z. and Sun, Nan}
}
