@article {8889451,
	title = {A Second-Order Purely VCO-Based CT $ΔΣ$ ADC Using a Modified DPLL Structure in 40-nm CMOS},
	journal = {IEEE Journal of Solid-State Circuits},
	volume = {55},
	number = {2},
	year = {2020},
	month = {Feb},
	pages = {356-368},
	abstract = {This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) ΔΣ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply.},
	issn = {1558-173X},
	doi = {10.1109/JSSC.2019.2948008},
	author = {Yi ZHONG and Li, Shaolan and Xiyuan TANG and Shen, Linxiao and Zhao, Wenda and Wu, Siliang and Sun, Nan}
}
