@article {8693795,
	title = {A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $ΔΣ$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO},
	journal = {IEEE Solid-State Circuits Letters},
	volume = {2},
	number = {1},
	year = {2019},
	month = {Jan},
	pages = {1-4},
	abstract = {This letter presents a high-speed closed-loop capacitive-input voltage controlled oscillators (VCO)-based continuous-time delta sigma modulator (CTDSM) using a novel fully differential VCO topology whose parasitic pole is inherently located at a very high frequency, regardless of the number of inverters in the ring VCO. The mitigation of the parasitic pole is achieved by splitting the VCO\&$\#$039;s input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO\&$\#$039;s input capacitance. A single pair of pseudo-resistors is used for providing dc negative feedback in the CTDSM. The prototype first-order 63-stage VCO-based CTDSM is fabricated in 40-nm CMOS and occupies a core area of 0.02 mm2 while achieving 63.1-dB dynamic range in 480 kHz-20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors\&$\#$039; best knowledge, this is also the first work to demonstrate the capacitive input in a high-speed CTDSM, without using chopping.},
	issn = {2573-9603},
	doi = {10.1109/LSSC.2019.2911874},
	author = {Mukherjee, Abhishek and Gandara, Miguel and Xu, Biying and Li, Shaolan and Shen, Linxiao and Xiyuan TANG and Pan, David and Sun, Nan}
}
