<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Zhou, Yuejia</style></author><author><style face="normal" font="default" size="100%">Ru HUANG</style></author><author><style face="normal" font="default" size="100%">Tang, Kechao</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A Novel Hybrid-FE-layer FeFET with Enhanced Linearity for On-chip Training of CIM Accelerator</style></title><secondary-title><style face="normal" font="default" size="100%">2024 8th IEEE Electron Devices Technology &amp;amp; Manufacturing Conference (EDTM)</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">Capacitors</style></keyword><keyword><style  face="normal" font="default" size="100%">Ferroelectric FET (FeFET)</style></keyword><keyword><style  face="normal" font="default" size="100%">iron</style></keyword><keyword><style  face="normal" font="default" size="100%">Linearity</style></keyword><keyword><style  face="normal" font="default" size="100%">Logic gates</style></keyword><keyword><style  face="normal" font="default" size="100%">neuromorphic computing</style></keyword><keyword><style  face="normal" font="default" size="100%">on-chip CIM</style></keyword><keyword><style  face="normal" font="default" size="100%">System-on-chip</style></keyword><keyword><style  face="normal" font="default" size="100%">Training</style></keyword><keyword><style  face="normal" font="default" size="100%">Voltage measurement</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2024</style></year></dates><pages><style face="normal" font="default" size="100%">1-3</style></pages><language><style face="normal" font="default" size="100%">eng</style></language></record></records></xml>