<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Li, Qiuhui</style></author><author><style face="normal" font="default" size="100%">Yang, Chen</style></author><author><style face="normal" font="default" size="100%">Xu, Lin</style></author><author><style face="normal" font="default" size="100%">Liu, Shiqi</style></author><author><style face="normal" font="default" size="100%">Fang, Shibo</style></author><author><style face="normal" font="default" size="100%">Xu, Linqiang</style></author><author><style face="normal" font="default" size="100%">Jie Yang</style></author><author><style face="normal" font="default" size="100%">Ma, Jiachen</style></author><author><style face="normal" font="default" size="100%">Ying Li</style></author><author><style face="normal" font="default" size="100%">Wu, Baochun</style></author><author><style face="normal" font="default" size="100%">Quhe, Ruge</style></author><author><style face="normal" font="default" size="100%">Tang, Kechao</style></author><author><style face="normal" font="default" size="100%">Jing Lu</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Symmetric and Excellent Scaling Behavior in Ultrathin n- and p-Type Gate-All-Around InAs Nanowire Transistors</style></title><secondary-title><style face="normal" font="default" size="100%">Advanced Functional Materials</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">gate-all-around transistors</style></keyword><keyword><style  face="normal" font="default" size="100%">quantum transport simulations</style></keyword><keyword><style  face="normal" font="default" size="100%">strain engineering</style></keyword><keyword><style  face="normal" font="default" size="100%">symmetric scaling behaviors</style></keyword><keyword><style  face="normal" font="default" size="100%">ultrathin InAs nanowires</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2023</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://onlinelibrary.wiley.com/doi/abs/10.1002/adfm.202214653</style></url></web-urls></urls><number><style face="normal" font="default" size="100%">n/a</style></number><volume><style face="normal" font="default" size="100%">n/a</style></volume><pages><style face="normal" font="default" size="100%">2214653</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">Abstract Complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility µe than silicon but suffers from a much lower hole mobility µh (µe/µh&amp;nbsp;= 80), thus unsuited to CMOS application with a single material. Through the accurate ab initio quantum-transport simulations, the performance gap between the NMOS and PMOS is significantly narrowed is predicted and even vanished in the sub-2-nm-diameter gate-all-around (GAA) InAs nanowires (NW) FETs because the inversion of the light and heavy hole bands occurs when the diameter is shorter than 3 nm. It is further proposed several feasible strategies for further improving the performance symmetry in the GAA InAs NWFETs. Short-channel effects are effectively depressed in the symmetric n- and p-type GAA InAs NWFETs till the gate length is scaled down to 2 nm according to the standards of the International Technology Roadmap for Semiconductors. Therefore, the ultrasmall GAA InAs NWFETs possess tremendous prospects in CMOS integrated circuits.</style></abstract></record></records></xml>