A Compact Writing Scheme for the Reliability Challenges in 1T Multi-level FeFET Array: Variation, Endurance and Write Disturb - Zhou, Yuejia; Shao, Hanyong; Huang, Weiqin; Zhu, Runteng; Zhang, Yihan; Ru HUANG; Tang, Kechao (IEEE Electron Device Letters, 2024)
Keywords: Costs; Electrons; endurance recovery; Error correction; FeFETs; iron; Logic gates; multi-level cell (MLC) FeFET; Performance evaluation; Reliability; tin; variation; write disturb; Writing; writing scheme