<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>10</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Maciej Kucharski</style></author><author><style face="normal" font="default" size="100%">Johannes Borngräber</style></author><author><style face="normal" font="default" size="100%">Defu Wang</style></author><author><style face="normal" font="default" size="100%">Dietmar Kissinger</style></author><author><style face="normal" font="default" size="100%">Herman Jalli Ng</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">A 109–137 GHz power amplifier in SiGe BiCMOS with 16.5 dBm output power and 12.8% PAE</style></title><secondary-title><style face="normal" font="default" size="100%">2017 47th European Microwave Conference (EuMC)</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2017</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://ieeexplore.ieee.org/abstract/document/8231020</style></url></web-urls></urls><publisher><style face="normal" font="default" size="100%">IEEE</style></publisher><pub-location><style face="normal" font="default" size="100%">Nuremberg, Germany</style></pub-location><pages><style face="normal" font="default" size="100%">1021-1024</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">This paper presents a 3-stage differential cascode power amplifier (PA) for 109–137 GHz applications. At 120 GHz the circuit delivers 16.5 dBm saturated output power with 12.8 % power-added efficiency (PAE) without using power combining techniques. The chip was fabricated in 130 nm SiGe BiCMOS technology offering heterojunction bipolar transistors (HBT) with f T /f max of 300/500 GHz. The PA consists of three stages optimized accordingly to the design goals. The first stage operates in class A to provide high gain while the two following stages are biased in class AB and deep class AB in order to increase the efficiency. The circuit draws a maximum current of 100 mA from 3.3 V and 4 V supplies. It occupies only 0.24 mm&amp;nbsp;2&amp;nbsp;chip area excluding baluns and bondpads, which makes it attractive for future power combiners. The presented amplifier is suitable for radar applications, that require a high dynamic range.</style></abstract></record></records></xml>